CS&E Profile: Pen-Chung Yew

High-performance and low-power multi-core architectures, compilation techniques that support multi-threading and speculation, dynamic compilation, binary translation, parallel machine organizations, and OS for multi-core embedded systems.

Ph.D. 1981, Computer Science, University of Illinois, Urbana-Champaign

M.S. 1977, Computer Engineering, University of Massachusetts, Amherst

B.S. 1972, Electrical Engineering, National Taiwan University

Research

My main research effort is on the design of future generations of high-performance and low-power computer systems, which include both microprocessors and multiprocessors. I am interested in issues related to their machine architectures, programming models, compilation techniques and system software.

In the design of future generations of microprocessors, we are focusing on multi-threaded, multi-core architectures that exploit both thread-level and instruction-level parallelism possibly with speculation support to achieve high performance with reduced power consumtion. The targeted systems span from large-scale parallel machines to application-specific embedded systems.

Our compiler effort is focused on a profile-based approach that supports both medium-grained (loop iteration-level) and fine-grained (instruction-level) parallelism with speculation, low power and latency hiding schemes. Research is focused on both static (at compile time) and dynamic (at runtime) compilation techniques. We also focus on binary translation techniques that support cross-platform execution. Another area of interests is on new parallel programming models that support domain experts for their specific applications.

System software research currently focuses on operating system support for multi-core embedded systems, and on supporting virtualization for various applications.

We use experimental approach to those design issues with on-going development of compiler and architectural simulation infrastructure to support our research effort.

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