Colloquia: Unleashing The Power of Software-Architecture Co-Design In Exascale Era and Beyond

March 19, 2018 -
11:15am to 12:15pm
Presenter: 
Affiliation: 
Pacific Northwest National Lab
Location: 
3-180 Keller Hall
Host: 
George Karypis

Biography: Shuaiwen Leon Song is currently a senior scientist and technical lead in High Performance Computing Group at Pacific Northwest National Lab (PNNL). He is a visiting scientist at Paul Allen department of Computer Science at University of Washington and an adjunct scholar with CS department at College of William & Mary. His research interests are in the areas of system efficiency, with a strong focus on software-architecture co-design in high performance computing. He is a Lawrence Livermore ISCR scholar, a recipient of 2011 Paul E. Torgersen excellent research award, 2016 PNNL PCSD outstanding performance award, and 2017 IEEE TCHPC early career award in high performance computing. He has published in major HPC-related conferences including ASPLOS, SC, MICRO, HPCA and PPoPP. His past works have received two best paper runner-up nominations in the Supercomputing conference and a HiPEAC paper award. His research has been supported by several U.S. government agencies and industry labs. Currently he is leading a big data analytics and a deep-learning directed HPC design LDRD project at PNNL.  

Abstract: Within a decade, the technological underpinnings for the process Gordon Moore described will likely come to an end as silicon photolithography approaches atomic scale. To continue the rapid, predictable, and affordable scaling of computing performance in exascale and beyond, major vendors have shown increased reliance on heterogeneous hardware acceleration, where multiple novel technologies are integrated into a single heterogeneous system, including different types of accelerators, new memory technologies and hybrid interconnect. Under such extreme heterogeneous environment, traditional software designs that do not consider these complex architecture features will no longer provide optimal efficiency. In this talk, I will use current commercial GPU-based heterogeneous architectures as examples to showcase my recent research related to co-design efforts, specifically on runtime-architecture co-design (e.g., circumventing architecture design constraints or leveraging its features to improve overall system efficiency), and application-architecture co-design (e.g., applying unique application features for design optimization steering). These two high-level topics cover a range of interesting co-design research directions such as approximate computing for scientific applications, big data analytics, 3D gaming/virtual reality, and emerging memory technology integration. I will also briefly discuss my ongoing projects in collaboration with academia and industry labs, as well as future research ideas.   

 

 

 

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