High-Level Information - An Approach for Integrating Front-End & Back-End Compilers
Date of Submission:
March 13, 1998
Existing compilers for automatically parallelizing application programs are often divided into parallelizing front-end compilers and optimizing back-end compilers. The front-end compilers perform high-level program analysis toidentify dependences among relatively coarse-grained program units, such as subroutines and loop iterations, and perform transformations on these large units. The back-end compilers, on the other hand, perform analyses andoptimizations on relatively finer-grained operations, such as machine instructions. Due to a lack of high-level information, however, the back-end compilers miss potential optimizations, and the scope of the optimizations islimited to only short-range local transformations. In this paper we propose a new universal High-Level Information (HLI) format to effectively integrate front-end and back-end compilers by passing front-end information to the back-end compiler. Importing this information into an existing back-end leverages the state-of-the-art analysis and transformation capabilities of existing front-end compilers to allow the back-end greater optimization potential than it has when relying on only locally-extracted information.A version of the HLI has been implemented in the SUIF parallelizing compiler and the GCC back-end compiler. Experimental results with the SPEC benchmarks show that HLI can provide GCC with substantially more accurate data dependence information than it can obtain on its own. Our results show that the number of dependence edges in GCC can be reduced by an average of 48% for the integer benchmark programs and an average of 54% for the floating-point benchmark programs studied, which provides greater flexibility to GCC's code scheduling pass. Even with the scheduling optimization limited to basic blocks,the use of HLI produces moderate speedups compared to using only GCC'sdependence tests, when the optimized programs are executed on MIPS R4600 and R10000 processors.