Design and Analysis of Architectures for Programmable Packet Processing Systems

April 4, 2003 -
10:15am to 11:15am
Location: 
EE/CS 3-125
Host: 
Wei-Chung Hsu
The rapid acceptance and explosive growth of computer networks have few parallels in the history of human technology. As the users and uses of interconnected networks have flourished, design requirements have changed rapidly. Increasingly, equipment vendors are pushed to provide networking equipment, such as routers, gateways and a host of other packet processing systems, with lower cost, higher performance
and greater flexibility. In response to these demands, vendors now build equipment around a new class of microprocessors, often called network processors. The potential benefits of this approach are clear:
if a commodity processor with sufficient performance is available,then vendors can avoid the increasing costs associated with producing custom integrated circuits, including design and skyrocketing mask
costs, while gaining the flexibility associated with software-based functionality. Despite these benefits, there are numerous challenges involved with designing and using such a processor.

In this talk, I will discuss two of these problems and present solutions taken from my dissertation work. First, I will present a study that explores the path to high-performance by quantifying the effectiveness of several modern microprocessor architectures -- namely, aggressive superscalar, fine-grain multithreaded, chip multiprocessor, and simultaneous multithreaded machines -- within the context of
networking. Second, I will motivate the need to design for worst-case conditions in networking systems, contrast this need with the practice of average-case analysis which dominates the design of general-purpose
systems, and describe a method that bounds the worst-case execution time of programs running on multithreaded network processors. I will conclude the talk with a look ahead to future work.

Bio

Patrick Crowley is currently a Ph.D. candidate in the Department of Computer Science and Engineering at the University of Washington. Before arriving in Seattle, he earned a B.A. degree, summa cum laude, from Illinois Wesleyan University where he studied
Mathematics, Physics and Computer Science. Crowley's research interests lie at the intersection of computer systems architecture and networking systems, with a present focus on the design and analysis of programmable packet processing systems. He is co-editor of, and contributing author to, the (currently) two-volume series of books entitled "Network Processor Design: Issues and Practices" from Morgan Kaufmann and is co-founder and co-organizer of the annual Workshop on Network Processors.